OpenRISC(1): First run OpenRISC on de0-nano board

The scope of the OpenRISC project is so extensive that it covers wild range of areas including processor architecture, implementation with register transfer language, simulation tool, synthesis tool, and tool-chain SDK. It is hard to believe the OpenRISC community behind this project has been able to put together the tremendous amount of efforts to successfully implement each single component, creating a valuable, well-performing, but free soft CPU for anyone to use.

As a newbie into this area, I quickly drown myself in the ocean of its ecosystem. Don’t worry if you are too, getting lost in the terms like IP core, fuseSoC, or1k, tool chain or openOCD. I spent quite a lot of time to sort out what role each of them plays in the big picture.

Instead of jumping into the details of them, I would rather show you how to quickly make it work on a de0-nano demo board. This way, I hope you will gain some confidence before burying yourself into much deeper pain.

First of all, you need to have a Linux machine to start with. Sorry, this is a must, especially you start from scratch. Once you have created a project with fuseSOC, you can move  to Winodows with no problem. is the starting point. Git check out the tutorial folder and run


You will have everything you need ready to go.

Then you will need the de0_nano development kit from Terasic. This board is officially supported in the OpenRISC tutorial. That means – you don’t need to change a single line of code to implement the CPU on this FPGA board.

Before you move on to the next command, you need to install the Altera Quartus IDE, as the FPGA on the de0_nano is Altera’s Cyclone IV E series. Make sure you have your Quartus bin folder in the path by adding the following line at the end of the ~/.profile.

export PATH=$PATH:/path_to/intelFPGA_lite/16.1/quartus/bin

Go to the folder tools/fusesoc/bin and run the following command:

fusesoc build de0_nano

So what happens next is fuseSoC, the awesome IP management program, will automatically put together all the necessary verilog HDL files and generate a Quartus project for the IDE software to compile. As a result, the Quartus will produce a SOF file for you to configure the FPGA on the de0_nano board. This process will take a quite while, you will see hundreds of lines of compile message print on your terminal.

If the build finishes without error, then you can run the build on a de0_nano board by:

fusesoc pgm de0_nano

Make sure your de0_nano board is connected to PC with a USB cable. You will notice that the JTAG indicator on the board will stay on during the programming. Once the FPGA is successfully configured, you should be able to see the onboard 8-bit LED indicators shifting from one to the next.

I assume you run all the above codes on Linux platform, you may run into errors as below:

Error (213019): Can't scan JTAG chain. Error code 87 ubuntu

That means your USB-Blaster driver either not installed correctly or lacks sufficient privilege. Please follow

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